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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-10 17:25:50 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-10 17:25:50 -0400 |
commit | aff3d92c007f7c971eed8417b1d7602394755398 (patch) | |
tree | 2055d7ec8c7c5532a68cdece5b30f18621075a5c /src/mem/cache/base_cache.cc | |
parent | 995146ead7bcf03b80bdea6281fa4a225ad48b72 (diff) | |
download | gem5-aff3d92c007f7c971eed8417b1d7602394755398.tar.xz |
Some more code cleanup
src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
--HG--
extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r-- | src/mem/cache/base_cache.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 0141fa2a0..4df13fb2b 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -221,6 +221,7 @@ BaseCache::CacheEvent::process() } else if (!cachePort->isCpuSide) { + assert(cachePort->cache->doMasterRequest()); //MSHR pkt = cachePort->cache->getPacket(); MSHR* mshr = (MSHR*) pkt->senderState; @@ -238,6 +239,7 @@ BaseCache::CacheEvent::process() } else { + assert(cachePort->cache->doSlaveRequest()); //CSHR pkt = cachePort->cache->getCoherencePacket(); bool success = cachePort->sendTiming(pkt); |