diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:04:59 -0400 |
---|---|---|
committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:04:59 -0400 |
commit | 54ed57cc4c0aab92cd5b3727c9def7667a49669d (patch) | |
tree | 9717a13c28584bfa6980df8246ca6c0ee7c5f342 /src/mem/cache/base_cache.cc | |
parent | a4c6f0d69eda5d23b12576080d532ddf768fbdbe (diff) | |
parent | 28e9641c2cf063d8ee1eba9f440dfcda9c82d965 (diff) | |
download | gem5-54ed57cc4c0aab92cd5b3727c9def7667a49669d.tar.xz |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/tport.cc:
Merge PacketPtr changes
--HG--
extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r-- | src/mem/cache/base_cache.cc | 27 |
1 files changed, 1 insertions, 26 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 6cbeef5a4..0694aae6e 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -115,32 +115,7 @@ BaseCache::CachePort::recvFunctional(PacketPtr pkt) // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) { - uint8_t* pkt_data; - uint8_t* write_data; - int data_size; - if (target->getAddr() < pkt->getAddr()) { - int offset = pkt->getAddr() - target->getAddr(); - pkt_data = pkt->getPtr<uint8_t>(); - write_data = target->getPtr<uint8_t>() + offset; - data_size = target->getSize() - offset; - assert(data_size > 0); - if (data_size > pkt->getSize()) - data_size = pkt->getSize(); - } else { - int offset = target->getAddr() - pkt->getAddr(); - pkt_data = pkt->getPtr<uint8_t>() + offset; - write_data = target->getPtr<uint8_t>(); - data_size = pkt->getSize() - offset; - assert(data_size >= pkt->getSize()); - if (data_size > target->getSize()) - data_size = target->getSize(); - } - - if (pkt->isWrite()) { - memcpy(pkt_data, write_data, data_size); - } else { - memcpy(write_data, pkt_data, data_size); - } + fixPacket(pkt, target); } } cache->doFunctionalAccess(pkt, isCpuSide); |