Fix up bus draining and add draining to the caches.

src/mem/bus.cc:
    Fix up draining to work properly.
src/mem/bus.hh:
    Initialize drainEvent to NULL.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Add draining to the caches.

--HG--
extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818

1 files changed, 22 insertions, 0 deletions

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 1c519fb86..c26d7782b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -140,6 +140,9 @@ BaseCache::CachePort::recvRetry()
             }
             waitingOnRetry = false;
         }
+        // Check if we're done draining once this list is empty
+        if (drainList.empty())
+            cache->checkDrain();
     }
     else if (!isCpuSide)
     {
@@ -338,6 +341,10 @@ BaseCache::CacheEvent::process()
         cachePort->drainList.push_back(pkt);
         cachePort->waitingOnRetry = true;
     }
+
+    // Check if we're done draining once this list is empty
+    if (cachePort->drainList.empty())
+        cachePort->cache->checkDrain();
 }
 
 const char *
@@ -599,3 +606,18 @@ BaseCache::regStats()
         ;
 
 }
+
+unsigned int
+BaseCache::drain(Event *de)
+{
+    // Set status
+    if (!canDrain()) {
+        drainEvent = de;
+
+        changeState(SimObject::Draining);
+        return 1;
+    }
+
+    changeState(SimObject::Drained);
+    return 0;
+}