diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:01:21 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-20 13:01:21 -0400 |
commit | 28e9641c2cf063d8ee1eba9f440dfcda9c82d965 (patch) | |
tree | 27d82f9251fe5b6eb5d4daa94c6b2af00f324229 /src/mem/cache/base_cache.cc | |
parent | 780aa0a0ebb765781a31d0fb58257b1efb1f324a (diff) | |
download | gem5-28e9641c2cf063d8ee1eba9f440dfcda9c82d965.tar.xz |
Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r-- | src/mem/cache/base_cache.cc | 27 |
1 files changed, 1 insertions, 26 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index e0301a757..c51f1b6ac 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -116,32 +116,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt) // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) { - uint8_t* pkt_data; - uint8_t* write_data; - int data_size; - if (target->getAddr() < pkt->getAddr()) { - int offset = pkt->getAddr() - target->getAddr(); - pkt_data = pkt->getPtr<uint8_t>(); - write_data = target->getPtr<uint8_t>() + offset; - data_size = target->getSize() - offset; - assert(data_size > 0); - if (data_size > pkt->getSize()) - data_size = pkt->getSize(); - } else { - int offset = target->getAddr() - pkt->getAddr(); - pkt_data = pkt->getPtr<uint8_t>() + offset; - write_data = target->getPtr<uint8_t>(); - data_size = pkt->getSize() - offset; - assert(data_size >= pkt->getSize()); - if (data_size > target->getSize()) - data_size = target->getSize(); - } - - if (pkt->isWrite()) { - memcpy(pkt_data, write_data, data_size); - } else { - memcpy(write_data, pkt_data, data_size); - } + fixPacket(pkt, target); } } cache->doFunctionalAccess(pkt, isCpuSide); |