Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.

Still need to rework upgrades into this system, but works for now.

src/mem/cache/base_cache.cc:
    Re order code to be more readable
src/mem/cache/base_cache.hh:
    Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
    Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
    Demorgans to make it easier to understand
src/mem/tport.cc:
    Delete writebacks

--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e

1 files changed, 10 insertions, 4 deletions

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 7a9e57430..8814abb38 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -525,8 +525,11 @@ class BaseCache : public MemObject
             reqCpu->schedule(time);
         }
         else {
-            if (pkt->cmd == Packet::Writeback) delete pkt->req;
-            delete pkt;
+            if (pkt->cmd != Packet::UpgradeReq)
+            {
+                delete pkt->req;
+                delete pkt;
+            }
         }
     }
 
@@ -545,8 +548,11 @@ class BaseCache : public MemObject
             reqCpu->schedule(time);
         }
         else {
-            if (pkt->cmd == Packet::Writeback) delete pkt->req;
-            delete pkt;
+            if (pkt->cmd != Packet::UpgradeReq)
+            {
+                delete pkt->req;
+                delete pkt;
+            }
         }
     }