diff options
| author | Kevin Lim <ktlim@umich.edu> | 2006-07-06 16:51:50 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-06 16:51:50 -0400 |
| commit | b55cda163ed1a29ee5e08cde36743047923ab475 (patch) | |
| tree | 3e94908acce5edfa05b76cf87a7d5b1ef012a720 /src/mem/cache/base_cache.hh | |
| parent | ec72f6534c2bb6aada305815fb306680508d7a7c (diff) | |
| parent | a1d208a65de95ee14c52fdc6ca9401642e07293d (diff) | |
| download | gem5-b55cda163ed1a29ee5e08cde36743047923ab475.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision : 7c7fc8a2f9579d443786e86dbcf906b355de69fc
Diffstat (limited to 'src/mem/cache/base_cache.hh')
| -rw-r--r-- | src/mem/cache/base_cache.hh | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 2754fab5a..5370a73c8 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -79,9 +79,9 @@ class BaseCache : public MemObject { class CachePort : public Port { + public: BaseCache *cache; - public: CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide); protected: @@ -110,10 +110,11 @@ class BaseCache : public MemObject struct CacheEvent : public Event { - Packet *pkt; CachePort *cachePort; + Packet *pkt; - CacheEvent(Packet *pkt, CachePort *cachePort); + CacheEvent(CachePort *_cachePort); + CacheEvent(CachePort *_cachePort, Packet *_pkt); void process(); const char *description(); }; @@ -147,6 +148,11 @@ class BaseCache : public MemObject fatal("No implementation"); } + virtual Packet *getPacket() + { + fatal("No implementation"); + } + /** * Bit vector of the blocking reasons for the access path. * @sa #BlockedCause @@ -388,7 +394,6 @@ class BaseCache : public MemObject if (!isBlockedForSnoop()) { memSidePort->clearBlocked(); } - } /** @@ -407,10 +412,13 @@ class BaseCache : public MemObject */ void setMasterRequest(RequestCause cause, Tick time) { + if (!doMasterRequest()) + { + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort); + reqCpu->schedule(time); + } uint8_t flag = 1<<cause; masterRequests |= flag; - assert("Implement\n" && 0); -// mi->pktuest(time); } /** @@ -462,8 +470,10 @@ class BaseCache : public MemObject */ void respond(Packet *pkt, Tick time) { - assert("Implement\n" && 0); -// si->respond(pkt,time); + pkt->makeTimingResponse(); + pkt->result = Packet::Success; + CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); + reqCpu->schedule(time); } /** @@ -476,8 +486,10 @@ class BaseCache : public MemObject if (!pkt->req->isUncacheable()) { missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time; } - assert("Implement\n" && 0); -// si->respond(pkt,time); + pkt->makeTimingResponse(); + pkt->result = Packet::Success; + CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); + reqCpu->schedule(time); } /** |