summaryrefslogtreecommitdiff
path: root/src/mem/cache/base_cache.hh
diff options
context:
space:
mode:
authorRon Dreslinski <rdreslin@umich.edu>2006-10-06 09:15:53 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-06 09:15:53 -0400
commit1b6653b6f791c87aeaf1dec98cdaa1a015cb11bd (patch)
treee9ee0240b2944c32ef2d05a6ebadb4678188bc02 /src/mem/cache/base_cache.hh
parent212c5aefb580375417d357d821255c67a8d90fdf (diff)
downloadgem5-1b6653b6f791c87aeaf1dec98cdaa1a015cb11bd.tar.xz
Remove threadnum from cache everywhere for now
Fix so that blocking for the same reason doesn't fail. I.E. multiple writebacks want to set the blocked flag. src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: Remove threadnum from cache everywhere for now --HG-- extra : convert_revision : 7890712147655280b4f1439d486feafbd5b18b2b
Diffstat (limited to 'src/mem/cache/base_cache.hh')
-rw-r--r--src/mem/cache/base_cache.hh18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 19cfe1335..7c16398aa 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -394,9 +394,12 @@ class BaseCache : public MemObject
blocked_causes[cause]++;
blockedCycle = curTick;
}
- blocked |= flag;
- DPRINTF(Cache,"Blocking for cause %s\n", cause);
- cpuSidePort->setBlocked();
+ if (!(blocked & flag)) {
+ //Wasn't already blocked for this cause
+ blocked |= flag;
+ DPRINTF(Cache,"Blocking for cause %s\n", cause);
+ cpuSidePort->setBlocked();
+ }
}
/**
@@ -407,8 +410,11 @@ class BaseCache : public MemObject
void setBlockedForSnoop(BlockedCause cause)
{
uint8_t flag = 1 << cause;
- blockedSnoop |= flag;
- memSidePort->setBlocked();
+ if (!(blocked & flag)) {
+ //Wasn't already blocked for this cause
+ blockedSnoop |= flag;
+ memSidePort->setBlocked();
+ }
}
/**
@@ -527,7 +533,7 @@ class BaseCache : public MemObject
void respondToMiss(Packet *pkt, Tick time)
{
if (!pkt->req->isUncacheable()) {
- missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
+ missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
}
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
reqCpu->schedule(time);