Fix some more mem leaks, still some left

Update retry mechanism

src/mem/cache/base_cache.cc:
    Rework the retry mechanism
src/mem/cache/base_cache.hh:
    Rework the retry mechanism
    Try to fix memory bug
src/mem/cache/cache_impl.hh:
    Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
    Fix mem leak on writebacks

--HG--
extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be

1 files changed, 11 insertions, 1 deletions

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index e0f12940f..41c28f3a1 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -112,6 +112,8 @@ class BaseCache : public MemObject
 
         bool isCpuSide;
 
+        bool waitingOnRetry;
+
         std::list<Packet *> drainList;
 
         Packet *cshrRetry;
@@ -465,7 +467,7 @@ class BaseCache : public MemObject
      */
     void setMasterRequest(RequestCause cause, Tick time)
     {
-        if (!doMasterRequest())
+        if (!doMasterRequest() && memSidePort->drainList.empty())
         {
             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
             reqCpu->schedule(time);
@@ -527,6 +529,10 @@ class BaseCache : public MemObject
             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
             reqCpu->schedule(time);
         }
+        else {
+            if (pkt->cmd == Packet::Writeback) delete pkt->req;
+            delete pkt;
+        }
     }
 
     /**
@@ -543,6 +549,10 @@ class BaseCache : public MemObject
             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
             reqCpu->schedule(time);
         }
+        else {
+            if (pkt->cmd == Packet::Writeback) delete pkt->req;
+            delete pkt;
+        }
     }
 
     /**