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authorNathan Binkert <binkertn@umich.edu>2006-10-20 00:10:12 -0700
committerNathan Binkert <binkertn@umich.edu>2006-10-20 00:10:12 -0700
commita4c6f0d69eda5d23b12576080d532ddf768fbdbe (patch)
tree72863fc8729c977d15d1c60aeb8243407e964550 /src/mem/cache/base_cache.hh
parent7245d4530d0c8367fa7b1adadcb55e1e8bd466e7 (diff)
downloadgem5-a4c6f0d69eda5d23b12576080d532ddf768fbdbe.tar.xz
Use PacketPtr everywhere
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
Diffstat (limited to 'src/mem/cache/base_cache.hh')
-rw-r--r--src/mem/cache/base_cache.hh32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 60d7029ac..565280aef 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -85,11 +85,11 @@ class BaseCache : public MemObject
CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -113,17 +113,17 @@ class BaseCache : public MemObject
bool waitingOnRetry;
- std::list<Packet *> drainList;
+ std::list<PacketPtr> drainList;
};
struct CacheEvent : public Event
{
CachePort *cachePort;
- Packet *pkt;
+ PacketPtr pkt;
CacheEvent(CachePort *_cachePort);
- CacheEvent(CachePort *_cachePort, Packet *_pkt);
+ CacheEvent(CachePort *_cachePort, PacketPtr _pkt);
void process();
const char *description();
};
@@ -141,17 +141,17 @@ class BaseCache : public MemObject
private:
//To be defined in cache_impl.hh not in base class
- virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+ virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
fatal("No implementation");
}
- virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
+ virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
fatal("No implementation");
}
- virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
+ virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
fatal("No implementation");
}
@@ -172,23 +172,23 @@ class BaseCache : public MemObject
}
}
- virtual Packet *getPacket()
+ virtual PacketPtr getPacket()
{
fatal("No implementation");
}
- virtual Packet *getCoherencePacket()
+ virtual PacketPtr getCoherencePacket()
{
fatal("No implementation");
}
- virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
+ virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
fatal("No implementation");
}
- virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success)
+ virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
fatal("No implementation");
@@ -519,7 +519,7 @@ class BaseCache : public MemObject
* @param pkt The request being responded to.
* @param time The time the response is ready.
*/
- void respond(Packet *pkt, Tick time)
+ void respond(PacketPtr pkt, Tick time)
{
if (pkt->needsResponse()) {
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
@@ -539,7 +539,7 @@ class BaseCache : public MemObject
* @param pkt The request to respond to.
* @param time The time the response is ready.
*/
- void respondToMiss(Packet *pkt, Tick time)
+ void respondToMiss(PacketPtr pkt, Tick time)
{
if (!pkt->req->isUncacheable()) {
missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
@@ -561,7 +561,7 @@ class BaseCache : public MemObject
* Suppliess the data if cache to cache transfers are enabled.
* @param pkt The bus transaction to fulfill.
*/
- void respondToSnoop(Packet *pkt, Tick time)
+ void respondToSnoop(PacketPtr pkt, Tick time)
{
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);