Fixes to get single level uni-coherence to work.

Now to try L2 caches in FS.

src/mem/cache/base_cache.hh:
    Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
    Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
    Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Properly forward invalidates in atomic/timing uni-coherence

--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7

1 files changed, 3 insertions, 1 deletions

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 93830b04f..60d7029ac 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -128,8 +128,10 @@ class BaseCache : public MemObject
         const char *description();
     };
 
-  protected:
+  public: //Made public so coherence can get at it.
     CachePort *cpuSidePort;
+
+  protected:
     CachePort *memSidePort;
 
     bool snoopRangesSent;