diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-13 15:47:05 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-13 15:47:05 -0400 |
commit | a17afb1649e26c248dc4a61e4a0ef6671785e992 (patch) | |
tree | af88a388d554563222a2612c938a1b8bdc1f2544 /src/mem/cache/base_cache.hh | |
parent | eddbb6801f6f9666d81cb5491b4ceedd3955f996 (diff) | |
download | gem5-a17afb1649e26c248dc4a61e4a0ef6671785e992.tar.xz |
Fix for DMA's in FS caches.
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
Diffstat (limited to 'src/mem/cache/base_cache.hh')
-rw-r--r-- | src/mem/cache/base_cache.hh | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 455e13d9c..7a9e57430 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -116,7 +116,6 @@ class BaseCache : public MemObject std::list<Packet *> drainList; - Packet *cshrRetry; }; struct CacheEvent : public Event @@ -188,6 +187,12 @@ class BaseCache : public MemObject fatal("No implementation"); } + virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success) + { + + fatal("No implementation"); + } + /** * Bit vector of the blocking reasons for the access path. * @sa #BlockedCause @@ -489,10 +494,13 @@ class BaseCache : public MemObject */ void setSlaveRequest(RequestCause cause, Tick time) { + if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry) + { + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(cpuSidePort); + reqCpu->schedule(time); + } uint8_t flag = 1<<cause; slaveRequests |= flag; - assert("Implement\n" && 0); -// si->pktuest(time); } /** |