Fix the packet data allocation methods. Small fixes from changesets after my initial work.

This now compiles.

src/mem/cache/base_cache.cc:
    Fix getPort function that changed
src/mem/cache/base_cache.hh:
    Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
    Fix virtual function declerations
src/mem/cache/cache_builder.cc:
    Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
    Properly allocate data in packet

--HG--
extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48

1 files changed, 21 insertions, 5 deletions

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 977e0ae29..2754fab5a 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -41,6 +41,7 @@
 #include <list>
 #include <inttypes.h>
 
+#include "base/misc.hh"
 #include "base/statistics.hh"
 #include "base/trace.hh"
 #include "mem/mem_object.hh"
@@ -122,14 +123,29 @@ class BaseCache : public MemObject
     CachePort *memSidePort;
 
   public:
-    virtual Port *getPort(const std::string &if_name);
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
 
   private:
     //To be defined in cache_impl.hh not in base class
-    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide);
-    virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
-    virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
-    virtual void recvStatusChange(Port::Status status, bool isCpuSide);
+    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
+
+    virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
+
+    virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
+
+    virtual void recvStatusChange(Port::Status status, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
 
     /**
      * Bit vector of the blocking reasons for the access path.