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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 14:35:00 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-06-28 14:35:00 -0400 |
commit | fc281d0b64fca8d2809ec462148acb7cf0461ea5 (patch) | |
tree | ef772f136f4e1bad0e9de6282201aa6611329fc7 /src/mem/cache/base_cache.hh | |
parent | ed8564a6b9f0702a40995d95cc4da54de3d35462 (diff) | |
download | gem5-fc281d0b64fca8d2809ec462148acb7cf0461ea5.tar.xz |
Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on
src/SConscript:
Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
Backing in more changsets, getting closer to compile
--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
Diffstat (limited to 'src/mem/cache/base_cache.hh')
-rw-r--r-- | src/mem/cache/base_cache.hh | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 0170b0249..977e0ae29 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -47,6 +47,7 @@ #include "mem/packet.hh" #include "mem/port.hh" #include "mem/request.hh" +#include "sim/eventq.hh" /** * Reasons for Caches to be Blocked. @@ -82,7 +83,7 @@ class BaseCache : public MemObject public: CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide); - private: + protected: virtual bool recvTiming(Packet *pkt); virtual Tick recvAtomic(Packet *pkt); @@ -96,6 +97,7 @@ class BaseCache : public MemObject virtual int deviceBlockSize(); + public: void setBlocked(); void clearBlocked(); @@ -110,10 +112,10 @@ class BaseCache : public MemObject Packet *pkt; CachePort *cachePort; - CacheResponseEvent(Packet *pkt, CachePort *cachePort); + CacheEvent(Packet *pkt, CachePort *cachePort); void process(); const char *description(); - } + }; protected: CachePort *cpuSidePort; @@ -124,7 +126,7 @@ class BaseCache : public MemObject private: //To be defined in cache_impl.hh not in base class - virtual bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide); + virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide); virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide); virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide); virtual void recvStatusChange(Port::Status status, bool isCpuSide); @@ -275,12 +277,14 @@ class BaseCache : public MemObject * of this cache. * @param params The parameter object for this BaseCache. */ - BaseCache(const std::string &name, HierParams *hier_params, Params ¶ms) - : BaseMem(name, hier_params, params.hitLatency, params.addrRange), - blocked(0), blockedSnoop(0), masterRequests(0), slaveRequests(0), - topLevelCache(false), blkSize(params.blkSize), + BaseCache(const std::string &name, Params ¶ms) + : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0), + slaveRequests(0), topLevelCache(false), blkSize(params.blkSize), missCount(params.maxMisses) { + //Start ports at null if more than one is created we should panic + cpuSidePort = NULL; + memSidePort = NULL; } /** @@ -453,8 +457,8 @@ class BaseCache : public MemObject */ void respondToMiss(Packet *pkt, Tick time) { - if (!pkt->isUncacheable()) { - missLatency[pkt->cmd.toIndex()][pkt->thread_num] += time - pkt->time; + if (!pkt->req->isUncacheable()) { + missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time; } assert("Implement\n" && 0); // si->respond(pkt,time); @@ -475,6 +479,11 @@ class BaseCache : public MemObject * to do for a cache. */ void rangeChange() {} + + void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) + { + panic("Unimplimented\n"); + } }; #endif //__BASE_CACHE_HH__ |