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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-12-02 06:08:17 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-12-02 06:08:17 -0500 |
| commit | 7ca27dd3ccc2bcd3b77480179030d07f50c3d2d9 (patch) | |
| tree | d663a1fc2e9797d90672656a9fd110df6d777ba6 /src/mem/cache/blk.hh | |
| parent | df37cad0fdf262ffbfd1b680e7fb8ef7689885ad (diff) | |
| download | gem5-7ca27dd3ccc2bcd3b77480179030d07f50c3d2d9.tar.xz | |
mem: Remove WriteInvalidate support
Prepare for a different implementation following in the next patch
Diffstat (limited to 'src/mem/cache/blk.hh')
| -rw-r--r-- | src/mem/cache/blk.hh | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index ff09b42c4..6c72817c0 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -73,9 +73,6 @@ enum CacheBlkStatusBits { BlkHWPrefetched = 0x20, /** block holds data from the secure memory space */ BlkSecure = 0x40, - /** can the block transition to E? (hasn't been shared with another cache) - * used to close a timing gap when handling WriteInvalidate packets */ - BlkCanGoExclusive = 0x80 }; /** |