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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-06-04 09:40:19 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-06-11 16:55:30 +0000
commitf54020eb8155371725ab75b0fc5c419287eca084 (patch)
tree65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/mem/cache/blk.hh
parent2113b21996d086dab32b9fd388efe3df241bfbd2 (diff)
downloadgem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/blk.hh')
-rw-r--r--src/mem/cache/blk.hh10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index c4ec12ff3..93189bd97 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -136,7 +136,7 @@ class CacheBlk : public ReplaceableEntry
// check for matching execution context, and an address that
// is within the lock
- bool matches(const RequestPtr req) const
+ bool matches(const RequestPtr &req) const
{
Addr req_low = req->getPaddr();
Addr req_high = req_low + req->getSize() -1;
@@ -145,7 +145,7 @@ class CacheBlk : public ReplaceableEntry
}
// check if a request is intersecting and thus invalidating the lock
- bool intersects(const RequestPtr req) const
+ bool intersects(const RequestPtr &req) const
{
Addr req_low = req->getPaddr();
Addr req_high = req_low + req->getSize() - 1;
@@ -153,7 +153,7 @@ class CacheBlk : public ReplaceableEntry
return (req_low <= highAddr) && (req_high >= lowAddr);
}
- Lock(const RequestPtr req)
+ Lock(const RequestPtr &req)
: contextId(req->contextId()),
lowAddr(req->getPaddr()),
highAddr(lowAddr + req->getSize() - 1)
@@ -285,7 +285,7 @@ class CacheBlk : public ReplaceableEntry
* Clear the any load lock that intersect the request, and is from
* a different context.
*/
- void clearLoadLocks(RequestPtr req)
+ void clearLoadLocks(const RequestPtr &req)
{
auto l = lockList.begin();
while (l != lockList.end()) {
@@ -357,7 +357,7 @@ class CacheBlk : public ReplaceableEntry
if (!pkt->isLLSC() && lockList.empty())
return true;
- RequestPtr req = pkt->req;
+ const RequestPtr &req = pkt->req;
if (pkt->isLLSC()) {
// it's a store conditional... have to check for matching