Revamp cache timing access mshr check to make stats sane again.

--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea

1 files changed, 16 insertions, 2 deletions

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index bafb46a89..127c547ac 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -51,8 +51,10 @@ enum CacheBlkStatusBits {
     BlkValid =		0x01,
     /** write permission */
     BlkWritable =	0x02,
+    /** read permission (yes, block can be valid but not readable) */
+    BlkReadable =	0x04,
     /** dirty (modified) */
-    BlkDirty =		0x04,
+    BlkDirty =		0x08,
     /** block was referenced */
     BlkReferenced =	0x10,
     /** block was a hardware prefetch yet unaccessed*/
@@ -162,7 +164,19 @@ class CacheBlk
     }
 
     /**
-     * Checks that a block is valid (readable).
+     * Checks the read permissions of this block.  Note that a block
+     * can be valid but not readable if there is an outstanding write
+     * upgrade miss.
+     * @return True if the block is readable.
+     */
+    bool isReadable() const
+    {
+        const int needed_bits = BlkReadable | BlkValid;
+        return (status & needed_bits) == needed_bits;
+    }
+
+    /**
+     * Checks that a block is valid.
      * @return True if the block is valid.
      */
     bool isValid() const