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| author | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
|---|---|---|
| committer | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
| commit | 6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch) | |
| tree | f23261eb3f3a7e91b08505e68015941b1d04ba7c /src/mem/cache/builder.cc | |
| parent | 74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff) | |
| download | gem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz | |
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'src/mem/cache/builder.cc')
| -rw-r--r-- | src/mem/cache/builder.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/cache/builder.cc b/src/mem/cache/builder.cc index ca8c378fb..6f1f841f8 100644 --- a/src/mem/cache/builder.cc +++ b/src/mem/cache/builder.cc @@ -71,7 +71,7 @@ using namespace std; #if defined(USE_CACHE_FALRU) #define BUILD_FALRU_CACHE do { \ - FALRU *tags = new FALRU(block_size, size, latency); \ + FALRU *tags = new FALRU(block_size, size, hit_latency); \ BUILD_CACHE(FALRU, tags); \ } while (0) #else @@ -80,7 +80,7 @@ using namespace std; #if defined(USE_CACHE_LRU) #define BUILD_LRU_CACHE do { \ - LRU *tags = new LRU(numSets, block_size, assoc, latency); \ + LRU *tags = new LRU(numSets, block_size, assoc, hit_latency); \ BUILD_CACHE(LRU, tags); \ } while (0) #else @@ -124,7 +124,7 @@ BaseCacheParams::create() iic_params.blkSize = block_size; iic_params.assoc = assoc; iic_params.hashDelay = hash_delay; - iic_params.hitLatency = latency; + iic_params.hitLatency = hit_latency; iic_params.rp = repl; iic_params.subblockSize = subblock_size; #else |