mem-cache: Move cache bypass mechanism to the ports

Cache bypass is necessary for cpu models like the KvmCPU. Previously
the bypass would happen at the cache classes. With this change the
bypassing happens directly at the ports.

Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62
Reviewed-on: https://gem5-review.googlesource.com/10432
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 0 insertions, 23 deletions

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index f74afcb2b..5034ca521 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -271,9 +271,6 @@ Cache::recvTimingSnoopResp(PacketPtr pkt)
 {
     DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
 
-    assert(pkt->isResponse());
-    assert(!system->bypassCaches());
-
     // determine if the response is from a snoop request we created
     // (in which case it should be in the outstandingSnoop), or if we
     // merely forwarded someone else's snoop request
@@ -409,16 +406,6 @@ Cache::recvTimingReq(PacketPtr pkt)
 {
     DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
 
-    assert(pkt->isRequest());
-
-    // Just forward the packet if caches are disabled.
-    if (system->bypassCaches()) {
-        // @todo This should really enqueue the packet rather
-        bool M5_VAR_USED success = memSidePort.sendTimingReq(pkt);
-        assert(success);
-        return;
-    }
-
     promoteWholeLineWrites(pkt);
 
     if (pkt->cacheResponding()) {
@@ -665,10 +652,6 @@ Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
 Tick
 Cache::recvAtomic(PacketPtr pkt)
 {
-    // Forward the request if the system is in cache bypass mode.
-    if (system->bypassCaches())
-        return ticksToCycles(memSidePort.sendAtomic(pkt));
-
     promoteWholeLineWrites(pkt);
 
     return BaseCache::recvAtomic(pkt);
@@ -1183,9 +1166,6 @@ Cache::recvTimingSnoopReq(PacketPtr pkt)
 {
     DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
 
-    // Snoops shouldn't happen when bypassing caches
-    assert(!system->bypassCaches());
-
     // no need to snoop requests that are not in range
     if (!inRange(pkt->getAddr())) {
         return;
@@ -1309,9 +1289,6 @@ Cache::recvTimingSnoopReq(PacketPtr pkt)
 Tick
 Cache::recvAtomicSnoop(PacketPtr pkt)
 {
-    // Snoops shouldn't happen when bypassing caches
-    assert(!system->bypassCaches());
-
     // no need to snoop requests that are not in range.
     if (!inRange(pkt->getAddr())) {
         return 0;