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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:21 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:21 -0500 |
commit | ac1368df50af123b32b41d7115ea4a0f15f7c97f (patch) | |
tree | 107ba41258ee0a30de841624bc6f3c5fab041d8f /src/mem/cache/cache.cc | |
parent | 2cb5467e8514934c4d88304c65050adead0ffc7e (diff) | |
download | gem5-ac1368df50af123b32b41d7115ea4a0f15f7c97f.tar.xz |
mem: Unify delayed packet deletion
This patch unifies how we deal with delayed packet deletion, where the
receiving slave is responsible for deleting the packet, but the
sending agent (e.g. a cache) is still relying on the pointer until the
call to sendTimingReq completes. Previously we used a mix of a
deletion vector and a construct using unique_ptr. With this patch we
ensure all slaves use the latter approach.
Diffstat (limited to 'src/mem/cache/cache.cc')
-rw-r--r-- | src/mem/cache/cache.cc | 29 |
1 files changed, 9 insertions, 20 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 3e5ed42bc..aa95d5604 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -542,15 +542,6 @@ bool Cache::recvTimingReq(PacketPtr pkt) { DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); -//@todo Add back in MemDebug Calls -// MemDebug::cacheAccess(pkt); - - - /// @todo temporary hack to deal with memory corruption issue until - /// 4-phase transactions are complete - for (int x = 0; x < pendingDelete.size(); x++) - delete pendingDelete[x]; - pendingDelete.clear(); assert(pkt->isRequest()); @@ -602,10 +593,9 @@ Cache::recvTimingReq(PacketPtr pkt) // main memory will delete the packet } - /// @todo nominally we should just delete the packet here, - /// however, until 4-phase stuff we can't because sending - /// cache is still relying on it. - pendingDelete.push_back(pkt); + // queue for deletion, as the sending cache is still relying + // on the packet + pendingDelete.reset(pkt); // no need to take any action in this particular cache as the // caches along the path to memory are allowed to keep lines @@ -678,12 +668,11 @@ Cache::recvTimingReq(PacketPtr pkt) // by access(), that calls accessBlock() function. cpuSidePort->schedTimingResp(pkt, request_time); } else { - /// @todo nominally we should just delete the packet here, - /// however, until 4-phase stuff we can't because sending cache is - /// still relying on it. If the block is found in access(), - /// CleanEvict and Writeback messages will be deleted here as - /// well. - pendingDelete.push_back(pkt); + // queue the packet for deletion, as the sending cache is + // still relying on it; if the block is found in access(), + // CleanEvict and Writeback messages will be deleted + // here as well + pendingDelete.reset(pkt); } } else { // miss @@ -754,7 +743,7 @@ Cache::recvTimingReq(PacketPtr pkt) // CleanEvicts corresponding to blocks which have outstanding // requests in MSHRs can be deleted here. if (pkt->cmd == MemCmd::CleanEvict) { - pendingDelete.push_back(pkt); + pendingDelete.reset(pkt); } else { DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", __func__, pkt->cmdString(), pkt->getAddr(), |