diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:07 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:07 -0600 |
| commit | 13ef7a56478fdd993a726833e14a85307446c28f (patch) | |
| tree | f347d4ecd903ba1d76fe90e2d7c5c9217af8c77d /src/mem/cache/cache.hh | |
| parent | 8c7936c40c7e63d7b8e11cc3d234fbe8de7d0f45 (diff) | |
| download | gem5-13ef7a56478fdd993a726833e14a85307446c28f.tar.xz | |
MEM: Differentiate functional cache accesses from CPU and memory
This patch changes the functionalAccess member function in the cache
model such that it is aware of what port the access came from, i.e. if
it came from the CPU side or from the memory side. By adding this
information, it is possible to respect the 'forwardSnoops' flag for
snooping requests coming from the memory side and not forward
them. This fixes an outstanding issue with the IO bus getting accesses
that have no valid destination port and also cleans up future changes
to the bus model.
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 1ed138bb5..8d30ed443 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * All rights reserved. * @@ -225,10 +237,9 @@ class Cache : public BaseCache /** * Performs the access specified by the request. * @param pkt The request to perform. - * @return The result of the access. + * @param fromCpuSide from the CPU side port or the memory side port */ - void functionalAccess(PacketPtr pkt, CachePort *incomingPort, - CachePort *otherSidePort); + void functionalAccess(PacketPtr pkt, bool fromCpuSide); /** * Handles a response (cache line fill/write ack) from the bus. |