Add ReadRespWithInvalidate to handle multi-level coherence situation

where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b

1 files changed, 2 insertions, 2 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4602fd835..170ba0cd1 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -186,7 +186,7 @@ class Cache : public BaseCache
     bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
 
     void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
-                                bool already_copied);
+                                bool already_copied, bool pending_inval);
 
     /**
      * Sets the blk to the new state.
@@ -194,7 +194,7 @@ class Cache : public BaseCache
      * @param new_state The new coherence state for the block.
      */
     void handleSnoop(PacketPtr ptk, BlkType *blk,
-                     bool is_timing, bool is_deferred);
+                     bool is_timing, bool is_deferred, bool pending_inval);
 
     /**
      * Create a writeback request for the given block.