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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:18 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:18 -0400 |
| commit | 71aca6d29e686ecdec2828c8be1989f74d9b28d3 (patch) | |
| tree | 1ff5b36c08f5e1c3853208674608d141e2924c57 /src/mem/cache/cache.hh | |
| parent | 7c4dc4491a6367888154129d2799b5f564ecb0d9 (diff) | |
| download | gem5-71aca6d29e686ecdec2828c8be1989f74d9b28d3.tar.xz | |
cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive
copies to higher levels (e.g., L1). This eliminates a lot
of unnecessary upgrade transactions on read-write sequences
to non-shared data.
Also some cleanup of MSHR coherence handling and multiple
bug fixes.
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 6cb6233f5..e15747c3f 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -178,7 +178,9 @@ class Cache : public BaseCache BlkType *handleFill(PacketPtr pkt, BlkType *blk, PacketList &writebacks); - void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); + void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, + bool deferred_response = false, + bool pending_downgrade = false); bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, @@ -292,7 +294,7 @@ class Cache : public BaseCache * are successfully sent. * @param pkt The request that was sent on the bus. */ - void markInService(MSHR *mshr); + void markInService(MSHR *mshr, PacketPtr pkt = 0); /** * Perform the given writeback request. |