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author | Lisa Hsu <hsul@eecs.umich.edu> | 2008-10-23 16:49:17 -0400 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2008-10-23 16:49:17 -0400 |
commit | 8788d703f81cef20916ffd2c7e0d28031cf65df8 (patch) | |
tree | 48795566574ac52ef9183f8ada9b60874df2bc04 /src/mem/cache/cache.hh | |
parent | 546a6c0c1b6dfc23bac1f74c6adec413931c6608 (diff) | |
download | gem5-8788d703f81cef20916ffd2c7e0d28031cf65df8.tar.xz |
s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
comments.
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r-- | src/mem/cache/cache.hh | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 510e67ba6..4db5230f8 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -137,7 +137,7 @@ class Cache : public BaseCache BlkType *tempBlock; /** - * Can this cache should allocate a block on a line-sized write miss. + * This cache should allocate a block on a line-sized write miss. */ const bool doFastWrites; @@ -149,8 +149,7 @@ class Cache : public BaseCache * @param lat The latency of the access. * @param writebacks List for any writebacks that need to be performed. * @param update True if the replacement data should be updated. - * @return Pointer to the cache block touched by the request. NULL if it - * was a miss. + * @return Boolean indicating whether the request was satisfied. */ bool access(PacketPtr pkt, BlkType *&blk, int &lat, PacketList &writebacks); |