Fixes to hitLatency, blocking, buffer allocation.

Single-cpu timing mode seems to work now.

--HG--
extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad

1 files changed, 0 insertions, 26 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 06fce1a71..a93b761ec 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -137,23 +137,6 @@ class Cache : public BaseCache
     BasePrefetcher *prefetcher;
 
     /**
-     * The clock ratio of the outgoing bus.
-     * Used for calculating critical word first.
-     */
-    int busRatio;
-
-     /**
-      * The bus width in bytes of the outgoing bus.
-      * Used for calculating critical word first.
-      */
-    int busWidth;
-
-    /**
-     * The latency of a hit in this device.
-     */
-    int hitLatency;
-
-    /**
      * Can this cache should allocate a block on a line-sized write miss.
      */
     const bool doFastWrites;
@@ -304,15 +287,6 @@ class Cache : public BaseCache
     void squash(int threadNum);
 
     /**
-     * Allocate a new MSHR or write buffer to handle a miss.
-     * @param pkt The access that missed.
-     * @param time The time to continue processing the miss.
-     * @param isFill Whether to fetch & allocate a block
-     *               or just forward the request.
-     */
-    MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus);
-
-    /**
      * Selects a outstanding request to service.
      * @return The request to service, NULL if none found.
      */