Fix the packet data allocation methods. Small fixes from changesets after my initial work.

This now compiles.

src/mem/cache/base_cache.cc:
    Fix getPort function that changed
src/mem/cache/base_cache.hh:
    Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
    Fix virtual function declerations
src/mem/cache/cache_builder.cc:
    Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
    Properly allocate data in packet

--HG--
extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48

1 files changed, 4 insertions, 4 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index d2af1d8bf..788715e76 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -146,16 +146,16 @@ class Cache : public BaseCache
     /** Instantiates a basic cache object. */
     Cache(const std::string &_name, Params &params);
 
-    bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
                         bool isCpuSide);
 
-    Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
+    virtual Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
                         bool isCpuSide);
 
-    void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
+    virtual void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
                             bool isCpuSide);
 
-    void recvStatusChange(Port::Status status, bool isCpuSide);
+    virtual void recvStatusChange(Port::Status status, bool isCpuSide);
 
     void regStats();