Still missing prefetch and tags directories as well as cache builder.

Some implementation details were left blank still, need to fill them in.

src/SConscript:
    Reorder build to compile all files first
src/mem/cache/cache.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
    More changesets pulled, now compiles everything in /miss directory and in the root directory
src/mem/packet.hh:
    Add some more support, need to clean some of it out once everything is working

--HG--
extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800

1 files changed, 26 insertions, 9 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 587faaf51..d2af1d8bf 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -44,8 +44,9 @@
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/prefetch/prefetcher.hh"
 
-// forward declarations
-class Bus;
+//Forward decleration
+class MSHR;
+
 
 /**
  * A template-policy based cache. The behavior of the cache can be altered by
@@ -92,6 +93,11 @@ class Cache : public BaseCache
       */
     int busWidth;
 
+    /**
+     * The latency of a hit in this device.
+     */
+    int hitLatency;
+
      /**
       * A permanent mem req to always be used to cause invalidations.
       * Used to append to target list, to cause an invalidation.
@@ -121,18 +127,18 @@ class Cache : public BaseCache
         bool doCopy;
         bool blockOnCopy;
         BaseCache::Params baseParams;
-        Bus *in;
-        Bus *out;
         Prefetcher<TagStore, Buffering> *prefetcher;
         bool prefetchAccess;
+        int hitLatency;
 
         Params(TagStore *_tags, Buffering *mq, Coherence *coh,
-               bool do_copy, BaseCache::Params params, Bus * in_bus,
-               Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
-               bool prefetch_access)
+               bool do_copy, BaseCache::Params params,
+               Prefetcher<TagStore, Buffering> *_prefetcher,
+               bool prefetch_access, int hit_latency)
             : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
-              blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
-              prefetcher(_prefetcher), prefetchAccess(prefetch_access)
+              blockOnCopy(false), baseParams(params),
+              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
+              hitLatency(hit_latency)
         {
         }
     };
@@ -140,6 +146,17 @@ class Cache : public BaseCache
     /** Instantiates a basic cache object. */
     Cache(const std::string &_name, Params &params);
 
+    bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+                        bool isCpuSide);
+
+    Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
+                        bool isCpuSide);
+
+    void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
+                            bool isCpuSide);
+
+    void recvStatusChange(Port::Status status, bool isCpuSide);
+
     void regStats();
 
     /**