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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:10:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:10:54 -0400 |
| commit | 88554790c34f6fef4ba6285927fb9742b90ab258 (patch) | |
| tree | 402fe474613aea36065f773f410d431637592955 /src/mem/cache/cache.hh | |
| parent | d17f5084ed93efd6bdb3ed46b2f81b9d1240af8c (diff) | |
| download | gem5-88554790c34f6fef4ba6285927fb9742b90ab258.tar.xz | |
Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.
The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.
As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 3c34c10f7..be81736aa 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -206,7 +206,7 @@ class Cache : public BaseCache * @return Boolean indicating whether the request was satisfied. */ bool access(PacketPtr pkt, BlkType *&blk, - int &lat, PacketList &writebacks); + Cycles &lat, PacketList &writebacks); /** *Handle doing the Compare and Swap function for SPARC. @@ -272,7 +272,7 @@ class Cache : public BaseCache /** * Performs the access specified by the request. * @param pkt The request to perform. - * @return The result of the access. + * @return The number of ticks required for the access. */ Tick atomicAccess(PacketPtr pkt); @@ -299,9 +299,9 @@ class Cache : public BaseCache * Snoop for the provided request in the cache and return the estimated * time of completion. * @param pkt The memory request to snoop - * @return The estimated completion time. + * @return The number of cycles required for the snoop. */ - Tick snoopAtomic(PacketPtr pkt); + Cycles snoopAtomic(PacketPtr pkt); /** * Squash all requests associated with specified thread. |