diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:01 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:01 -0400 |
| commit | 06a9f58c68b621f082d39299bdb01f59ef68ef0e (patch) | |
| tree | 51d9b7982e124d9acccdd8e8fdd8cecf96c0f83f /src/mem/cache/cache.hh | |
| parent | 5c38668ed68fae7ed18571571d7855b541c4b039 (diff) | |
| download | gem5-06a9f58c68b621f082d39299bdb01f59ef68ef0e.tar.xz | |
DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.
--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 57028a05e..821fa9702 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -72,7 +72,8 @@ class Cache : public BaseCache { public: CpuSidePort(const std::string &_name, - Cache<TagStore> *_cache); + Cache<TagStore> *_cache, + std::vector<Range<Addr> > filterRanges); // BaseCache::CachePort just has a BaseCache *; this function // lets us get back the type info we lost when we stored the @@ -95,7 +96,8 @@ class Cache : public BaseCache { public: MemSidePort(const std::string &_name, - Cache<TagStore> *_cache); + Cache<TagStore> *_cache, + std::vector<Range<Addr> > filterRanges); // BaseCache::CachePort just has a BaseCache *; this function // lets us get back the type info we lost when we stored the |