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| author | Steve Reinhardt <Steve.Reinhardt@amd.com> | 2008-07-16 11:10:33 -0700 |
|---|---|---|
| committer | Steve Reinhardt <Steve.Reinhardt@amd.com> | 2008-07-16 11:10:33 -0700 |
| commit | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (patch) | |
| tree | 22e2bc30405ba483ac571951f49cc77d7e713477 /src/mem/cache/cache.hh | |
| parent | 05d8c9acb8a5a985956998fc13551288496e5cdc (diff) | |
| download | gem5-6629d9b2bc58a885bfebce1517fd12483497b6e4.tar.xz | |
mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 4570b067b..6cb6233f5 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -71,8 +71,7 @@ class Cache : public BaseCache public: CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, - const std::string &_label, - std::vector<Range<Addr> > filterRanges); + const std::string &_label); // BaseCache::CachePort just has a BaseCache *; this function // lets us get back the type info we lost when we stored the @@ -96,8 +95,7 @@ class Cache : public BaseCache public: MemSidePort(const std::string &_name, Cache<TagStore> *_cache, - const std::string &_label, - std::vector<Range<Addr> > filterRanges); + const std::string &_label); // BaseCache::CachePort just has a BaseCache *; this function // lets us get back the type info we lost when we stored the |