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authorRon Dreslinski <rdreslin@umich.edu>2006-06-28 17:28:33 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-06-28 17:28:33 -0400
commit0d323c753d897bec72884089bc0dc334a64e9eb3 (patch)
treeb5c69c91860b1282cf2ef8a415ce965e51d94f4f /src/mem/cache/cache.hh
parentfc281d0b64fca8d2809ec462148acb7cf0461ea5 (diff)
downloadgem5-0d323c753d897bec72884089bc0dc334a64e9eb3.tar.xz
More Changes, working towards cache.cc compiling. Headers cleaned up.
src/mem/cache/cache_blk.hh: Remove XC --HG-- extra : convert_revision : aa2c43e4412ebb93165e12f693d5126983cfd0dc
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r--src/mem/cache/cache.hh7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 78e87479b..587faaf51 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -138,7 +138,7 @@ class Cache : public BaseCache
};
/** Instantiates a basic cache object. */
- Cache(const std::string &_name, HierParams *hier_params, Params &params);
+ Cache(const std::string &_name, Params &params);
void regStats();
@@ -147,7 +147,7 @@ class Cache : public BaseCache
* @param req The request to perform.
* @return The result of the access.
*/
- MemAccessResult access(Packet * &pkt);
+ bool access(Packet * &pkt);
/**
* Selects a request to send on the bus.
@@ -233,7 +233,8 @@ class Cache : public BaseCache
*/
void respond(Packet * &pkt, Tick time)
{
- si->respond(pkt,time);
+ //si->respond(pkt,time);
+ cpuSidePort->sendAtomic(pkt);
}
/**