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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-04 09:10:53 -0800 |
| commit | 5fbf3aa47112b3d28971c0bab604ce9cc3f67b16 (patch) | |
| tree | f38e2827f802c205d8373d68d125a8d17aa5e4ee /src/mem/cache/cache.hh | |
| parent | 51e3688701fe66987f96c5ddc5b8f111f4ad94d6 (diff) | |
| download | gem5-5fbf3aa47112b3d28971c0bab604ce9cc3f67b16.tar.xz | |
Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.
--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 1f3b087bb..29502042c 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -42,6 +42,7 @@ #include "cpu/smt.hh" // SMT_MAX_THREADS #include "mem/cache/base_cache.hh" +#include "mem/cache/miss/miss_buffer.hh" #include "mem/cache/prefetch/prefetcher.hh" //Forward decleration @@ -55,7 +56,7 @@ class MSHR; * @sa MissQueue. Coherence handles all coherence policy details @sa * UniCoherence, SimpleMultiCoherence. */ -template <class TagStore, class Buffering, class Coherence> +template <class TagStore, class Coherence> class Cache : public BaseCache { public: @@ -68,12 +69,12 @@ class Cache : public BaseCache /** Tag and data Storage */ TagStore *tags; /** Miss and Writeback handler */ - Buffering *missQueue; + MissBuffer *missQueue; /** Coherence protocol. */ Coherence *coherence; /** Prefetcher */ - Prefetcher<TagStore, Buffering> *prefetcher; + Prefetcher<TagStore> *prefetcher; /** * The clock ratio of the outgoing bus. @@ -105,16 +106,16 @@ class Cache : public BaseCache { public: TagStore *tags; - Buffering *missQueue; + MissBuffer *missQueue; Coherence *coherence; BaseCache::Params baseParams; - Prefetcher<TagStore, Buffering> *prefetcher; + Prefetcher<TagStore> *prefetcher; bool prefetchAccess; int hitLatency; - Params(TagStore *_tags, Buffering *mq, Coherence *coh, + Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, BaseCache::Params params, - Prefetcher<TagStore, Buffering> *_prefetcher, + Prefetcher<TagStore> *_prefetcher, bool prefetch_access, int hit_latency) : tags(_tags), missQueue(mq), coherence(coh), baseParams(params), |