mem: write streaming support via WriteInvalidate promotion

Support full-block writes directly rather than requiring RMW:
 * a cache line is allocated in the cache upon receipt of a
   WriteInvalidateReq, not the WriteInvalidateResp.
 * only top-level caches allocate the line; the others just pass
   the request along and invalidate as necessary.
 * to close a timing window between the *Req and the *Resp, a new
   metadata bit tracks whether another cache has read a copy of
   the new line before the writeback to memory.

1 files changed, 5 insertions, 0 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 0ee1e353a..12fb3b0f0 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -181,6 +181,11 @@ class Cache : public BaseCache
     const bool doFastWrites;
 
     /**
+     * Turn line-sized writes into WriteInvalidate transactions.
+     */
+    void promoteWholeLineWrites(PacketPtr pkt);
+
+    /**
      * Notify the prefetcher on every access, not just misses.
      */
     const bool prefetchOnAccess;