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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-27 04:56:01 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-27 04:56:01 -0400
commit24763c21775aed939228b1c8f048f8f7982de91c (patch)
treebaf9be0d8d0cdbb96e0154a6d0d61be8250a0abf /src/mem/cache/cache.hh
parenta7a1e6004a0d2508913277b5c60d245fdcad2681 (diff)
downloadgem5-24763c21775aed939228b1c8f048f8f7982de91c.tar.xz
mem: Cleanup flow for uncacheable accesses
This patch simplifies the code dealing with uncacheable timing accesses, aiming to align it with the existing miss handling. Similar to what we do in atomic, a timing request now goes through Cache::access (where the block is also flushed), and then proceeds to ignore any existing MSHR for the block in question. This unifies the flow for cacheable and uncacheable accesses, and for atomic and timing.
Diffstat (limited to 'src/mem/cache/cache.hh')
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