diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-18 08:16:22 -0700 |
---|---|---|
committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-18 08:16:22 -0700 |
commit | 6cd187e1f066b084740b4b202f1de644ba06f299 (patch) | |
tree | 32db5b9458ccf1d39669b94693baff56afbb47d2 /src/mem/cache/cache.hh | |
parent | 0128b73d0588ecdf66fcb482fddad2853216edce (diff) | |
download | gem5-6cd187e1f066b084740b4b202f1de644ba06f299.tar.xz |
Get rid of obsolete in-cache copy support.
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r-- | src/mem/cache/cache.hh | 41 |
1 files changed, 3 insertions, 38 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 7024ce58a..07d9d6336 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -75,12 +75,6 @@ class Cache : public BaseCache /** Prefetcher */ Prefetcher<TagStore, Buffering> *prefetcher; - /** Do fast copies in this cache. */ - bool doCopy; - - /** Block on a delayed copy. */ - bool blockOnCopy; - /** * The clock ratio of the outgoing bus. * Used for calculating critical word first. @@ -105,18 +99,6 @@ class Cache : public BaseCache Packet * invalidatePkt; Request *invalidateReq; - /** - * Temporarily move a block into a MSHR. - * @todo Remove this when LSQ/SB are fixed and implemented in memtest. - */ - void pseudoFill(Addr addr); - - /** - * Temporarily move a block into an existing MSHR. - * @todo Remove this when LSQ/SB are fixed and implemented in memtest. - */ - void pseudoFill(MSHR *mshr); - public: class Params @@ -125,19 +107,17 @@ class Cache : public BaseCache TagStore *tags; Buffering *missQueue; Coherence *coherence; - bool doCopy; - bool blockOnCopy; BaseCache::Params baseParams; Prefetcher<TagStore, Buffering> *prefetcher; bool prefetchAccess; int hitLatency; Params(TagStore *_tags, Buffering *mq, Coherence *coh, - bool do_copy, BaseCache::Params params, + BaseCache::Params params, Prefetcher<TagStore, Buffering> *_prefetcher, bool prefetch_access, int hit_latency) - : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy), - blockOnCopy(false), baseParams(params), + : tags(_tags), missQueue(mq), coherence(coh), + baseParams(params), prefetcher(_prefetcher), prefetchAccess(prefetch_access), hitLatency(hit_latency) { @@ -192,21 +172,6 @@ class Cache : public BaseCache void handleResponse(Packet * &pkt); /** - * Start handling a copy transaction. - * @param pkt The copy request to perform. - */ - void startCopy(Packet * &pkt); - - /** - * Handle a delayed copy transaction. - * @param pkt The delayed copy request to continue. - * @param addr The address being responded to. - * @param blk The block of the current response. - * @param mshr The mshr being handled. - */ - void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr); - - /** * Selects a coherence message to forward to lower levels of the hierarchy. * @return The coherence message to forward. */ |