MEM: Split SimpleTimingPort into PacketQueue and ports

This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).

As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.

The PioPort and MessagePort are cleaned up as part of the changes.

--HG--
rename : src/mem/tport.cc => src/mem/packet_queue.cc
rename : src/mem/tport.hh => src/mem/packet_queue.hh

1 files changed, 31 insertions, 5 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 288395584..782749aab 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -109,6 +109,34 @@ class Cache : public BaseCache
     };
 
     /**
+     * Override the default behaviour of sendDeferredPacket to enable
+     * the memory-side cache port to also send requests based on the
+     * current MSHR status. This queue has a pointer to our specific
+     * cache implementation and is used by the MemSidePort.
+     */
+    class MemSidePacketQueue : public PacketQueue
+    {
+
+      protected:
+
+        Cache<TagStore> &cache;
+
+      public:
+
+        MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
+                           const std::string &label) :
+            PacketQueue(cache, port, label), cache(cache) { }
+
+        /**
+         * Override the normal sendDeferredPacket and do not only
+         * consider the transmit list (used for responses), but also
+         * requests.
+         */
+        virtual void sendDeferredPacket();
+
+    };
+
+    /**
      * The memory-side port extends the base cache master port with
      * access functions for functional, atomic and timing snoops.
      */
@@ -116,6 +144,9 @@ class Cache : public BaseCache
     {
       private:
 
+        /** The cache-specific queue. */
+        MemSidePacketQueue _queue;
+
         // a pointer to our specific cache implementation
         Cache<TagStore> *cache;
 
@@ -134,11 +165,6 @@ class Cache : public BaseCache
 
         MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
                     const std::string &_label);
-
-        /**
-         * Overload sendDeferredPacket of SimpleTimingPort.
-         */
-        virtual void sendDeferredPacket();
     };
 
     /** Tag and data Storage */