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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-13 22:04:36 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-12-13 22:04:36 -0800 |
commit | d172e1576a9d8fd422d881c8f72a9c5cc4b6b9a6 (patch) | |
tree | 93bfd057e44d9c450d0c1103d668de9ec9dda8fc /src/mem/cache/cache.hh | |
parent | 98bb1c62b31e988f81d9fc03cf14aca25fd008db (diff) | |
download | gem5-d172e1576a9d8fd422d881c8f72a9c5cc4b6b9a6.tar.xz |
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r-- | src/mem/cache/cache.hh | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 29502042c..097b0f513 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -64,8 +64,49 @@ class Cache : public BaseCache typedef typename TagStore::BlkType BlkType; bool prefetchAccess; + protected: + class CpuSidePort : public CachePort + { + public: + CpuSidePort(const std::string &_name, + Cache<TagStore,Coherence> *_cache); + + // BaseCache::CachePort just has a BaseCache *; this function + // lets us get back the type info we lost when we stored the + // cache pointer there. + Cache<TagStore,Coherence> *myCache() { + return static_cast<Cache<TagStore,Coherence> *>(cache); + } + + virtual bool recvTiming(PacketPtr pkt); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvFunctional(PacketPtr pkt); + }; + + class MemSidePort : public CachePort + { + public: + MemSidePort(const std::string &_name, + Cache<TagStore,Coherence> *_cache); + + // BaseCache::CachePort just has a BaseCache *; this function + // lets us get back the type info we lost when we stored the + // cache pointer there. + Cache<TagStore,Coherence> *myCache() { + return static_cast<Cache<TagStore,Coherence> *>(cache); + } + + virtual bool recvTiming(PacketPtr pkt); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvFunctional(PacketPtr pkt); + }; + /** Tag and data Storage */ TagStore *tags; /** Miss and Writeback handler */ @@ -128,12 +169,7 @@ class Cache : public BaseCache /** Instantiates a basic cache object. */ Cache(const std::string &_name, Params ¶ms); - virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, - bool isCpuSide); - - virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide); - - virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide); + virtual Port *getPort(const std::string &if_name, int idx = -1); virtual void recvStatusChange(Port::Status status, bool isCpuSide); |