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authorSteve Reinhardt <steve.reinhardt@amd.com>2009-02-16 08:56:40 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2009-02-16 08:56:40 -0800
commit89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (patch)
tree53a9b0877112908b1f6c3e5cad256a9b63a5de16 /src/mem/cache/cache.hh
parent6923282fb5a9ba6af14d19be094839eefe1c34be (diff)
downloadgem5-89a7fb03934b3e38c7d8b2c4818794b3ec874fdf.tar.xz
Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r--src/mem/cache/cache.hh12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4db5230f8..4570b067b 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -64,8 +64,6 @@ class Cache : public BaseCache
/** A typedef for a list of BlkType pointers. */
typedef typename TagStore::BlkList BlkList;
- bool prefetchAccess;
-
protected:
class CpuSidePort : public CachePort
@@ -141,7 +139,10 @@ class Cache : public BaseCache
*/
const bool doFastWrites;
- const bool prefetchMiss;
+ /**
+ * Notify the prefetcher on every access, not just misses.
+ */
+ const bool prefetchOnAccess;
/**
* Does all the processing necessary to perform the provided request.
@@ -320,6 +321,11 @@ class Cache : public BaseCache
bool inMissQueue(Addr addr) {
return (mshrQueue.findMatch(addr) != 0);
}
+
+ /**
+ * Find next request ready time from among possible sources.
+ */
+ Tick nextMSHRReadyTime();
};
#endif // __CACHE_HH__