Fix for DMA's in FS caches.

Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)

Now both timing/atomic caches with MOESI in UP fail at same point.

src/dev/io_device.hh:
    DMA's should send WriteInvalidates
src/mem/bridge.cc:
    Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Fix CSHR's for flow control.
src/mem/packet.hh:
    Make a writeInvalidateResp, since the DMA expects responses to it's writes

--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd

1 files changed, 7 insertions, 0 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 41b270030..7024ce58a 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -179,6 +179,13 @@ class Cache : public BaseCache
     virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
 
     /**
+     * Was the CSHR request was sent successfully?
+     * @param pkt The request.
+     * @param success True if the request was sent successfully.
+     */
+    virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
+
+    /**
      * Handles a response (cache line fill/write ack) from the bus.
      * @param pkt The request being responded to.
      */