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author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-15 18:07:39 -0500 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-15 18:07:39 -0500 |
commit | 4da37bcd1bc2c42ce5f297a58b4b4bffa4e8cd4f (patch) | |
tree | 3b149ecf699e5c16e3a9ab6af0e37fe3c2fd4c63 /src/mem/cache/cache.hh | |
parent | 956e673c55abaf85f9e419d0964799643ef14f02 (diff) | |
parent | d172e1576a9d8fd422d881c8f72a9c5cc4b6b9a6 (diff) | |
download | gem5-4da37bcd1bc2c42ce5f297a58b4b4bffa4e8cd4f.tar.xz |
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r-- | src/mem/cache/cache.hh | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 29502042c..097b0f513 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -64,8 +64,49 @@ class Cache : public BaseCache typedef typename TagStore::BlkType BlkType; bool prefetchAccess; + protected: + class CpuSidePort : public CachePort + { + public: + CpuSidePort(const std::string &_name, + Cache<TagStore,Coherence> *_cache); + + // BaseCache::CachePort just has a BaseCache *; this function + // lets us get back the type info we lost when we stored the + // cache pointer there. + Cache<TagStore,Coherence> *myCache() { + return static_cast<Cache<TagStore,Coherence> *>(cache); + } + + virtual bool recvTiming(PacketPtr pkt); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvFunctional(PacketPtr pkt); + }; + + class MemSidePort : public CachePort + { + public: + MemSidePort(const std::string &_name, + Cache<TagStore,Coherence> *_cache); + + // BaseCache::CachePort just has a BaseCache *; this function + // lets us get back the type info we lost when we stored the + // cache pointer there. + Cache<TagStore,Coherence> *myCache() { + return static_cast<Cache<TagStore,Coherence> *>(cache); + } + + virtual bool recvTiming(PacketPtr pkt); + + virtual Tick recvAtomic(PacketPtr pkt); + + virtual void recvFunctional(PacketPtr pkt); + }; + /** Tag and data Storage */ TagStore *tags; /** Miss and Writeback handler */ @@ -128,12 +169,7 @@ class Cache : public BaseCache /** Instantiates a basic cache object. */ Cache(const std::string &_name, Params ¶ms); - virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, - bool isCpuSide); - - virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide); - - virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide); + virtual Port *getPort(const std::string &if_name, int idx = -1); virtual void recvStatusChange(Port::Status status, bool isCpuSide); |