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| author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-15 13:06:37 -0500 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-15 13:06:37 -0500 |
| commit | b93b32ec3395971631467cb6116e278f6f205c90 (patch) | |
| tree | 194d336cdf736a7972c7fe4b36803a45d48a9a62 /src/mem/cache/cache.hh | |
| parent | 573d59441e420f02fd7cf3e31158258f5eee3ab1 (diff) | |
| parent | 98bb1c62b31e988f81d9fc03cf14aca25fd008db (diff) | |
| download | gem5-b93b32ec3395971631467cb6116e278f6f205c90.tar.xz | |
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
Diffstat (limited to 'src/mem/cache/cache.hh')
| -rw-r--r-- | src/mem/cache/cache.hh | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 1f3b087bb..29502042c 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -42,6 +42,7 @@ #include "cpu/smt.hh" // SMT_MAX_THREADS #include "mem/cache/base_cache.hh" +#include "mem/cache/miss/miss_buffer.hh" #include "mem/cache/prefetch/prefetcher.hh" //Forward decleration @@ -55,7 +56,7 @@ class MSHR; * @sa MissQueue. Coherence handles all coherence policy details @sa * UniCoherence, SimpleMultiCoherence. */ -template <class TagStore, class Buffering, class Coherence> +template <class TagStore, class Coherence> class Cache : public BaseCache { public: @@ -68,12 +69,12 @@ class Cache : public BaseCache /** Tag and data Storage */ TagStore *tags; /** Miss and Writeback handler */ - Buffering *missQueue; + MissBuffer *missQueue; /** Coherence protocol. */ Coherence *coherence; /** Prefetcher */ - Prefetcher<TagStore, Buffering> *prefetcher; + Prefetcher<TagStore> *prefetcher; /** * The clock ratio of the outgoing bus. @@ -105,16 +106,16 @@ class Cache : public BaseCache { public: TagStore *tags; - Buffering *missQueue; + MissBuffer *missQueue; Coherence *coherence; BaseCache::Params baseParams; - Prefetcher<TagStore, Buffering> *prefetcher; + Prefetcher<TagStore> *prefetcher; bool prefetchAccess; int hitLatency; - Params(TagStore *_tags, Buffering *mq, Coherence *coh, + Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, BaseCache::Params params, - Prefetcher<TagStore, Buffering> *_prefetcher, + Prefetcher<TagStore> *_prefetcher, bool prefetch_access, int hit_latency) : tags(_tags), missQueue(mq), coherence(coh), baseParams(params), |