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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:30:24 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:30:24 -0700 |
commit | d69a763833f911cb2d7f97604108219b4da0b881 (patch) | |
tree | 538d12c555824c931a3ceaedea5a2f46aa4e5212 /src/mem/cache/cache_builder.cc | |
parent | c2a97387cf543061bdb02f5259875b10a4dd6f74 (diff) | |
parent | 35cf19d441ed15d054d00674ec67ab5bc769f6d7 (diff) | |
download | gem5-d69a763833f911cb2d7f97604108219b4da0b881.tar.xz |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
configs/example/memtest.py:
Hand merge redundant changes.
--HG--
extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
Diffstat (limited to 'src/mem/cache/cache_builder.cc')
-rw-r--r-- | src/mem/cache/cache_builder.cc | 33 |
1 files changed, 6 insertions, 27 deletions
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index e887f711e..307c851a2 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -70,12 +70,7 @@ #include "base/compression/null_compression.hh" #include "base/compression/lzss_compression.hh" -// MissQueue Templates -#include "mem/cache/miss/miss_queue.hh" -#include "mem/cache/miss/blocking_buffer.hh" - // Coherence Templates -#include "mem/cache/coherence/uni_coherence.hh" #include "mem/cache/coherence/simple_coherence.hh" //Prefetcher Headers @@ -208,13 +203,9 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) else { \ BUILD_NULL_PREFETCHER(TAGS); \ } \ - Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \ + Cache<TAGS, c>::Params params(tags, coh, base_params, \ pf, prefetch_access, latency, \ true, \ - store_compressed, \ - adaptive_compression, \ - compressed_bus, \ - compAlg, compression_latency, \ prefetch_miss); \ Cache<TAGS, c> *retval = \ new Cache<TAGS, c>(getInstanceName(), params); \ @@ -302,13 +293,6 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) } while (0) #define BUILD_COHERENCE(b) do { \ - if (protocol == NULL) { \ - UniCoherence *coh = new UniCoherence(); \ - BUILD_CACHES(UniCoherence); \ - } else { \ - SimpleCoherence *coh = new SimpleCoherence(protocol); \ - BUILD_CACHES(SimpleCoherence); \ - } \ } while (0) #if defined(USE_TAGGED) @@ -375,8 +359,9 @@ CREATE_SIM_OBJECT(BaseCache) } // Build BaseCache param object - BaseCache::Params base_params(addr_range, latency, - block_size, max_miss_count); + BaseCache::Params base_params(latency, block_size, + mshrs, tgts_per_mshr, write_buffers, + max_miss_count); //Warnings about prefetcher policy if (pf_policy == "none" && (prefetch_miss || prefetch_access)) { @@ -414,14 +399,8 @@ CREATE_SIM_OBJECT(BaseCache) const void *repl = NULL; #endif - if (mshrs == 1 /*|| out_bus->doEvents() == false*/) { - BlockingBuffer *mq = new BlockingBuffer(true); - BUILD_COHERENCE(BlockingBuffer); - } else { - MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers, - true, prefetch_miss); - BUILD_COHERENCE(MissQueue); - } + SimpleCoherence *coh = new SimpleCoherence(protocol); + BUILD_CACHES(SimpleCoherence); return NULL; } |