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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:01 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:01 -0400 |
| commit | 06a9f58c68b621f082d39299bdb01f59ef68ef0e (patch) | |
| tree | 51d9b7982e124d9acccdd8e8fdd8cecf96c0f83f /src/mem/cache/cache_builder.cc | |
| parent | 5c38668ed68fae7ed18571571d7855b541c4b039 (diff) | |
| download | gem5-06a9f58c68b621f082d39299bdb01f59ef68ef0e.tar.xz | |
DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.
--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
Diffstat (limited to 'src/mem/cache/cache_builder.cc')
| -rw-r--r-- | src/mem/cache/cache_builder.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 4c9592a1b..0f8b52af2 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -241,7 +241,8 @@ BaseCacheParams::create() // Build BaseCache param object BaseCache::Params base_params(latency, block_size, mshrs, tgts_per_mshr, write_buffers, - max_miss_count); + max_miss_count, cpu_side_filter_ranges, + mem_side_filter_ranges); //Warnings about prefetcher policy if (prefetch_policy == Enums::none) { |