Fixes to hitLatency, blocking, buffer allocation.

Single-cpu timing mode seems to work now.

--HG--
extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad

1 files changed, 24 insertions, 32 deletions

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 81fcb4158..0649b5061 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -150,27 +150,6 @@ Cache<TagStore,Coherence>::cmpAndSwap(BlkType *blk, PacketPtr pkt)
 
 
 template<class TagStore, class Coherence>
-MSHR *
-Cache<TagStore,Coherence>::allocateBuffer(PacketPtr pkt, Tick time,
-                                          bool requestBus)
-{
-    MSHRQueue *mq = NULL;
-
-    if (pkt->isWrite() && !pkt->isRead()) {
-        /**
-         * @todo Add write merging here.
-         */
-        mq = &writeBuffer;
-    } else {
-        mq = &mshrQueue;
-    }
-
-    return allocateBufferInternal(mq, pkt->getAddr(), pkt->getSize(),
-                                  pkt, time, requestBus);
-}
-
-
-template<class TagStore, class Coherence>
 void
 Cache<TagStore,Coherence>::markInService(MSHR *mshr)
 {
@@ -438,6 +417,8 @@ Cache<TagStore,Coherence>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
         return NULL;
     }
 
+    assert(cpu_pkt->needsResponse());
+
     MemCmd cmd;
     const bool useUpgrades = true;
     if (blkValid && useUpgrades) {
@@ -1043,23 +1024,34 @@ Cache<TagStore,Coherence>::getTimingPacket()
         return NULL;
     }
 
-    BlkType *blk = tags->findBlock(mshr->addr);
-
     // use request from 1st target
     PacketPtr tgt_pkt = mshr->getTarget()->pkt;
-    PacketPtr pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive);
+    PacketPtr pkt = NULL;
 
-    mshr->isCacheFill = (pkt != NULL);
-
-    if (pkt == NULL) {
-        // make copy of current packet to forward
-        pkt = new Packet(tgt_pkt);
-        pkt->allocate();
-        if (pkt->isWrite()) {
-            pkt->setData(tgt_pkt->getPtr<uint8_t>());
+    if (mshr->isSimpleForward()) {
+        // no response expected, just forward packet as it is
+        assert(tags->findBlock(mshr->addr) == NULL);
+        pkt = tgt_pkt;
+    } else {
+        BlkType *blk = tags->findBlock(mshr->addr);
+        pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive);
+
+        mshr->isCacheFill = (pkt != NULL);
+
+        if (pkt == NULL) {
+            // not a cache block request, but a response is expected
+            assert(!mshr->isSimpleForward());
+            // make copy of current packet to forward, keep current
+            // copy for response handling
+            pkt = new Packet(tgt_pkt);
+            pkt->allocate();
+            if (pkt->isWrite()) {
+                pkt->setData(tgt_pkt->getPtr<uint8_t>());
+            }
         }
     }
 
+    assert(pkt != NULL);
     pkt->senderState = mshr;
     return pkt;
 }