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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
commit | 6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch) | |
tree | f8815e56c08a92059b5d576728f564c7bfce7bf0 /src/mem/cache/cache_impl.hh | |
parent | c4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff) | |
parent | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff) | |
download | gem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz |
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index e4e4a3c92..0b2b273f9 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -216,7 +216,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, if (blk->isDirty()) { // special considerations if we're owner: - if (!deferred_response) { + if (!deferred_response && !isTopLevel) { // if we are responding immediately and can // signal that we're transferring ownership // along with exclusivity, do so |