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author | Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) <mitch.hayenga+gem5@gmail.com> | 2014-01-29 23:21:25 -0600 |
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committer | Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E) <mitch.hayenga+gem5@gmail.com> | 2014-01-29 23:21:25 -0600 |
commit | 95735e10e7ea85320ee39c15a4132eece8417af4 (patch) | |
tree | 370863ea1bb2413937c03218e0b59aecc7a76fbe /src/mem/cache/cache_impl.hh | |
parent | 32cc2ea8b9173863adeaa03f4d7ee1635acfdef7 (diff) | |
download | gem5-95735e10e7ea85320ee39c15a4132eece8417af4.tar.xz |
mem: prefetcher: add options, support for unaligned addresses
This patch extends the classic prefetcher to work on non-block aligned
addresses. Because the existing prefetchers in gem5 mask off the lower
address bits of cache accesses, many predictable strides fail to be
detected. For example, if a load were to stride by 48 bytes, with 64 byte
cachelines, the current stride based prefetcher would see an access pattern
of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This
patch fixes this, by training the prefetcher on access and not masking off the
lower address bits.
It also adds the following configuration options:
1) Training/prefetching only on cache misses,
2) Training/prefetching only on data acceses,
3) Optionally tagging prefetches with a PC address.
#3 allows prefetchers to train off of prefetch requests in systems with
multiple cache levels and PC-based prefetchers present at multiple levels.
It also effectively allows a pipelining of prefetch requests (like in POWER4)
across multiple levels of cache hierarchy.
Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean).
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index b26473336..76fb697c2 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -556,6 +556,17 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt) // move it ahead of mshrs that are ready // mshrQueue.moveToFront(mshr); } + + // We should call the prefetcher reguardless if the request is + // satisfied or not, reguardless if the request is in the MSHR or + // not. The request could be a ReadReq hit, but still not + // satisfied (potentially because of a prior write to the same + // cache line. So, even when not satisfied, tehre is an MSHR + // already allocated for this, we need to let the prefetcher know + // about the request + if (prefetcher) { + next_pf_time = prefetcher->notify(pkt, time); + } } else { // no MSHR assert(pkt->req->masterId() < system->maxMasters()); |