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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/mem/cache/cache_impl.hh | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r-- | src/mem/cache/cache_impl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 16b5148dc..fbab8465e 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1006,7 +1006,8 @@ Cache<TagStore>::writebackBlk(BlkType *blk) writebacks[0/*pkt->req->threadId()*/]++; Request *writebackReq = - new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0); + new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, + Request::wbMasterId); PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1); if (blk->isWritable()) { writeback->setSupplyExclusive(); |