diff options
| author | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
| commit | 64295b800fd67e9b9bb3eee0131511a71ddf1fdb (patch) | |
| tree | ed1c759f11384dd2c263b43d7842be2922c5c39d /src/mem/cache/cache_impl.hh | |
| parent | b92594dd90f54a892771989a8164148e6647c9ab (diff) | |
| parent | ec4000e0e284834df0eb1db792074a1b11f21cc8 (diff) | |
| download | gem5-64295b800fd67e9b9bb3eee0131511a71ddf1fdb.tar.xz | |
merge
--HG--
extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index d144266ed..402e34db2 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -39,6 +39,7 @@ #include "sim/host.hh" #include "base/misc.hh" +#include "base/range_ops.hh" #include "mem/cache/cache.hh" #include "mem/cache/cache_blk.hh" @@ -61,8 +62,10 @@ Cache<TagStore>::Cache(const std::string &_name, tempBlock = new BlkType(); tempBlock->data = new uint8_t[blkSize]; - cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this); - memSidePort = new MemSidePort(_name + "-mem_side_port", this); + cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this, + params.baseParams.cpuSideFilterRanges); + memSidePort = new MemSidePort(_name + "-mem_side_port", this, + params.baseParams.memSideFilterRanges); cpuSidePort->setOtherPort(memSidePort); memSidePort->setOtherPort(cpuSidePort); @@ -88,7 +91,8 @@ Cache<TagStore>::getPort(const std::string &if_name, int idx) } else if (if_name == "mem_side") { return memSidePort; } else if (if_name == "functional") { - return new CpuSidePort(name() + "-cpu_side_funcport", this); + return new CpuSidePort(name() + "-cpu_side_funcport", this, + std::vector<Range<Addr> >()); } else { panic("Port name %s unrecognized\n", if_name); } @@ -1221,6 +1225,7 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) // CPU side port doesn't snoop; it's a target only. bool dummy; otherPort->getPeerAddressRanges(resp, dummy); + FilterRangeList(filterRanges, resp); snoop = false; } @@ -1262,8 +1267,9 @@ Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt) template<class TagStore> Cache<TagStore>:: CpuSidePort::CpuSidePort(const std::string &_name, - Cache<TagStore> *_cache) - : BaseCache::CachePort(_name, _cache) + Cache<TagStore> *_cache, std::vector<Range<Addr> > + filterRanges) + : BaseCache::CachePort(_name, _cache, filterRanges) { } @@ -1279,6 +1285,8 @@ Cache<TagStore>::MemSidePort:: getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { otherPort->getPeerAddressRanges(resp, snoop); + FilterRangeList(filterRanges, resp); + // Memory-side port always snoops, so unconditionally set flag for // caller. snoop = true; @@ -1416,8 +1424,9 @@ Cache<TagStore>::MemSidePort::processSendEvent() template<class TagStore> Cache<TagStore>:: -MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache) - : BaseCache::CachePort(_name, _cache) +MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache, + std::vector<Range<Addr> > filterRanges) + : BaseCache::CachePort(_name, _cache, filterRanges) { // override default send event from SimpleTimingPort delete sendEvent; |