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authorMitch Hayenga <mitch.hayenga@arm.com>2014-12-23 09:31:18 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2014-12-23 09:31:18 -0500
commitdf82a2d00311b96ec7fefc901232ba01bbf26d39 (patch)
treeef7d4ac6cc316d9a67eada5df423d32cef97173d /src/mem/cache/cache_impl.hh
parent6cb58b2bd2ffd19a667e3b9473ff4a0ccfd14c81 (diff)
downloadgem5-df82a2d00311b96ec7fefc901232ba01bbf26d39.tar.xz
mem: Rework the structuring of the prefetchers
Re-organizes the prefetcher class structure. Previously the BasePrefetcher forced multiple assumptions on the prefetchers that inherited from it. This patch makes the BasePrefetcher class truly representative of base functionality. For example, the base class no longer enforces FIFO order. Instead, prefetchers with FIFO requests (like the existing stride and tagged prefetchers) now inherit from a new QueuedPrefetcher base class. Finally, the stride-based prefetcher now assumes a custimizable lookup table (sets/ways) rather than the previous fully associative structure.
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
-rw-r--r--src/mem/cache/cache_impl.hh10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index da04cf6f9..15e9bc0fb 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -535,7 +535,7 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
bool satisfied = access(pkt, blk, lat, writebacks);
// track time of availability of next prefetch, if any
- Tick next_pf_time = 0;
+ Tick next_pf_time = MaxTick;
bool needsResponse = pkt->needsResponse();
@@ -548,7 +548,7 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
- next_pf_time = prefetcher->notify(pkt, time);
+ next_pf_time = prefetcher->notify(pkt);
}
if (needsResponse) {
@@ -648,7 +648,7 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
if (prefetcher) {
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
- next_pf_time = prefetcher->notify(pkt, time);
+ next_pf_time = prefetcher->notify(pkt);
}
}
} else {
@@ -688,12 +688,12 @@ Cache<TagStore>::recvTimingReq(PacketPtr pkt)
if (prefetcher) {
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
- next_pf_time = prefetcher->notify(pkt, time);
+ next_pf_time = prefetcher->notify(pkt);
}
}
}
- if (next_pf_time != 0)
+ if (next_pf_time != MaxTick)
requestMemSideBus(Request_PF, std::max(time, next_pf_time));
// copy writebacks to write buffer