diff options
| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-12-23 09:31:18 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-12-23 09:31:18 -0500 |
| commit | 6cb58b2bd2ffd19a667e3b9473ff4a0ccfd14c81 (patch) | |
| tree | 013ae71318955157fc22fa174655f681383bac92 /src/mem/cache/cache_impl.hh | |
| parent | 4d88978913c57e0cd10751d31d7f5b95c1e00170 (diff) | |
| download | gem5-6cb58b2bd2ffd19a667e3b9473ff4a0ccfd14c81.tar.xz | |
mem: Add parameter to reserve MSHR entries for demand access
Adds a new parameter that reserves some number of MSHR entries for demand
accesses. This helps prevent prefetchers from taking all MSHRs, forcing demand
requests from the CPU to stall.
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index f9eacb897..da04cf6f9 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1841,7 +1841,7 @@ Cache<TagStore>::getNextMSHR() // fall through... no pending requests. Try a prefetch. assert(!miss_mshr && !write_mshr); - if (prefetcher && !mshrQueue.isFull()) { + if (prefetcher && mshrQueue.canPrefetch()) { // If we have a miss queue slot, we can try a prefetch PacketPtr pkt = prefetcher->getPacket(); if (pkt) { |