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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:07:15 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:07:15 -0400 |
| commit | 74546aac0124a5ba09a0e6bfef18dc3e0b7509b8 (patch) | |
| tree | 367e2fbfa58d670c2a91076f080c998e69f4eeb6 /src/mem/cache/cache_impl.hh | |
| parent | 741bc40cc336be6afdff73a230eaec980812b7d5 (diff) | |
| download | gem5-74546aac0124a5ba09a0e6bfef18dc3e0b7509b8.tar.xz | |
Cleaned up include files and got rid of many using directives in header files.
--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index a447ae3d5..56e7a4d58 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -53,8 +53,6 @@ #include "sim/sim_events.hh" // for SimExitEvent -using namespace std; - template<class TagStore, class Buffering, class Coherence> bool Cache<TagStore,Buffering,Coherence>:: @@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid()); // There can be many matching outstanding writes. - vector<MSHR*> writes; + std::vector<MSHR*> writes; missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes); if (!update) { |